The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device in which a structure of a trenched capacitor is improved.
In recent semiconductor memory devices such as a dynamic memory, a memory capacity thereof has increased four times in three years in accordance with advances in micropatterning techniques. Memory cell area has rapidly become smaller in proportion to a large memory capacity. However, a capacitance of a capacitor of the memory cell must be maintained to be a sufficiently large value of several tens of fF in order to keep a proper S/N ratio for preventing a soft error and for sensing by a sense amplifier.
In order to increase a capacitance per unit area, an insulation film of a metal oxide semiconductor (MOS) structure for the memory capacitor can be rendered thin, or a silicon nitride film can be used as an insulation film material instead of a silicon oxide film. However, since the memory capacitor having a MOS structure is formed on a semiconductor substrate, a capacitance thereof is limited in accordance with micropatterning of the cell area.
Thus, H. Sunami et al. proposed a MOS memory cell having a corrugated capacitor of a structure shown in FIG. 1 which is described in detail in "A Corrugated Capacitor Cell (CCC) for Megabit Dynamic MOS Memories," International Electric Devices Meeting Technical Digest, Lecture No. 26.9, pp. 806 to 808, Dec. 1982. In FIG. 1, reference numeral 1 denotes a p-type silicon substrate. A deep groove 2 (e.g., about 3 to 5 .mu.m) is formed so as to extend from a surface of the substrate 1 to a certain depth inside thereof. A capacitor electrode 3 formed of a first polycrystalline silicon layer is insulated by a capacitor insulation film 4 and extends from the groove 2 to a level above an opening thereof. The capacitor insulation film 4 has a three-layered structure of SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2. The substrate 1, the groove 2, the capacitor insulation film 4 and the capacitor electrode 3 constitute a trenched capacitor 5. N.sup.+ -type source and drain regions 6 and 7 which are electrically isolated from each other are formed in a surface region of the silicon substrate 1 near the trenched capacitor 5. A gate electrode 9 formed of a second polycrystalline silicon layer is formed on a gate oxide film 8 in a region of substrate 1 between the source and drain regions 6 and 7. A transfer transistor 10 consists of the source and drain regions 6 and 7, the gate oxide film 8 and the gate electrode 9. Furthermore, the source region 6 is in contact with the insulation film 4 of the trenched capacitor 5, and the drain region 7 is connected to a bit line (not shown). In FIG. 1, reference numeral 9' denotes a gate electrode of an adjacent memory cell.
The MOS memory shown in FIG. 1 has a structure wherein an inversion layer of an interface between the capacitor insulation film 4 of the trenched capacitor 5 and the semiconductor substrate 1 serves as one electrode, and this electrode is connected to the source region 6 of the transfer transistor 10 so as to form a charge accumulation node of the memory cell. In this structure, a data holding time of the memory cell, that is, a pause time is not long enough. This is because the groove 2 which defines the inversion layer serving as one electrode has a large surface area. For this reason, a leakage current flows into the semiconductor substrate, thereby causing memory data loss. In addition to this, a surface of a portion of the semiconductor substrate 1 which defines the groove 2 is roughened by a dry etching process when the groove 2 is formed or is roughened by defects caused by a mechanical stress which is applied upon the groove 2. Thus, the leakage current into the semiconductor substrate 1 is increased, resulting in memory data loss.
In the MOS memory cell shown in FIG. 1, as described above, when one trenched capacitor of two adjacent memory cells is formed near that of the other cell, a punch through phenomenon easily occurs, thereby causing an interference of data. For this reason, a distance between the trenched capacitors of the two adjacent cells cannot be shortened beyond a certain limit. As a result, a high-density memory cell cannot be realized. Furthermore, a junction capacitance between the drain and the substrate of the transfer transistor which constructs the memory cell must be decreased in order to reduce a bit line capacitance. For this reason, an impurity concentration of the p-type silicon substrate must be decreased. However, a depletion layer is then easily formed in a region of the substrate near the capacitor of the MOS structure, thus causing the punch-through phenomenon. The punch-through phenomenon can be prevented to a certain extent by ion-implanting impurity ions in the silicon substrate. However, as shown in FIG. 1, in the trenched capacitor 5 in which the deep groove 2 is formed in the silicon substrate 1, it is difficult to ion-implant an impurity into a deep section of the silicon substrate 1. For this reason, the punch-through phenomenon easily occurs between the bottom portions of the two adjacent trenched capacitors. Therefore, in the conventional structure, the trenched capacitors of the two adjacent memory cells must be spaced apart by a large distance, thus preventing a high-density memory from being realized.
Furthermore, in the structure shown in FIG. 1, since the depletion layer extends from the trenched capacitor 5 in a deep section of the silicon substrate 1, electric charges generated by irradiation of an .alpha.-ray can easily concentrate by a funneling phenomenon, and a soft error easily occurs.